1. Field of the Invention
The present invention relates to circuits for reversible computation, and more particularly to a static combinatorial adiabatic switching CMOS logic structure for reversible computation.
2. Description of the Background Art
U.S. Pat. No. 5,241,221, issued Aug. 31, 1993 to Fletcher et al entitled "CMOS DRIVER CIRCUIT HAVING REDUCED SWITCHING NOISE" discloses a driver circuit wherein high and low impedance drive means respond to a threshold value of the output signal and turn off the low-impedance drive means in the course of the output transition. The low initial output impedance of the driver circuit effects rapid charging of a line capacitance, while toward the end of the output transition the higher output impedance of the driver circuit more closely matches the input impedance of a load circuit. This higher impedance dampens ringing and thereby reduces induced supply line noise which is conventionally associated with high-speed driver circuits.
U.S. Pat. No. 5,175,447 issued Dec. 29, 1992 to Kawaski et al entitled "MULTIFUNCTIONAL SCAN FLIP-FLOP" discloses a multifunctional scan flip-flop having a normal function and a scan function, including: a first latch used for a normal function for latching input data applied to a data input terminal during a normal function operation, the latch operation being carried out synchronous with a clock applied to a clock input terminal; a second latch used for a scan function for holding scan data applied to a scan data input terminal during a scan function operation; and a delay circuit for delaying one of the input data and the clock relative to the other, the delay operation being carried out in accordance with the H/L level of the scan data held by the second latch.
U.S. Pat. No. 5,134,320 issued Jul. 28, 1992 to Perusse entitled "HIGH EFFICIENCY FET DRIVER WITH ENERGY RECOVERY" discloses a circuit incorporating a circuit element for recovering the energy stored in the parasitic input capacitance of a power transistor at turn-on. The circuit includes a resonating element, such as a transformer, and a diode coupled between a voltage source and a power transistor, such as a field effect transistor. The diode is adapted to avoid loading of the power source. The energy is recovered and stored until a new turn-on interval is required or until there is a need for other power requirements. This improves the operating efficiency of a system using the circuit. For a given loss, the recovery of this energy permits operation at a higher frequency or size reduction and/or improved performance, or the use of large die for reduced conduction loss. The advantages are the same for FETs when they are used as the control element or as a rectifier element, but the gains in efficiency are most notable in rectifier applications.
U.S. Pat. No. 4,707,620 issued Nov. 17, 1987 to Sullivan et al. entitled "ADJUSTABLE IMPEDANCE DRIVER NETWORK" discloses a variable impedance driver network that comprises a plurality of transmission gates connected in parallel between a voltage source and an output. Each transmission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.
U.S. Pat. No. 3,980,897 issued Sept. 14, 1976 to Arnold entitled "LOGIC GATING SYSTEM AND METHOD" discloses a circuit arrangement that has a first subset of semiconductor devices, an associated first additional device and a first gate output. A second subset of semiconductor devices has an associated second additional device and a second gate output. The first and second subsets are of one conductivity type while the first and second additional devices are of another conductivity type. First logic signals are applied to the first subset for turning on the first subset and the first additional device for producing at the first gate output a first function of the first logic signals. Second logic signals are applied to the second subset for turning on the second subset and the second additional device for producing at the second gate output a second function of the second logic signals.
The publication "An Electroid Switching Model For Reversible Computer Architectures," by J. S. Hall, Proc. Workshop on Physics and Computation, Oct. 1992 (IEEE Comp. Soc. Press, 1993, p. 237 describes electronic implementations using adiabatic switching and "electroid switches".